Logic devices such as field programmable gate arrays (FPGAs) are used to implement large systems that may include million of gates and megabits of embedded memory. The complexity of large systems often requires the use of electronic design automation (EDA) tools to create and optimize a design for the system onto physical target devices. Among the procedures performed by EDA tools in a computer aided design (CAD) flow are synthesis, placement, and routing.
Timing analysis is an important aspect of design that allows the EDA tools to determine whether certain synthesis, placement, and/or routing decisions allow a design to satisfy system timing requirements. If a particular synthesis, placement, and/or routing decision does not satisfy system timing requirements, alternate strategies may be explored and/or notification may be provided to the system designer. Timing analysis may be performed during or after synthesis, placement, and routing.
In efforts to reduce power dissipation of systems, EDA tools attempt to identify the lowest supply voltages that systems can operate on target devices while still satisfying system timing requirements. Generally, the finer the level of granularity of testable supply voltages are available to static timing analyzers, the more optimal a solution can be found by the static timing analyzers. Most static timing analyzers, however, limit the supply voltages that are testable to discrete values. The current source driver model for performing static timing analysis requires models of circuit elements at all testable supply voltages. The size of memory storage limits the number of such models that can be made available.